My researches on Multiple-Valued are divided into two periods

From 1974 to 1994

1974-1979

• Design of a ternary bipolar inverter
• Characteristics and models of multivalued circuits. Definition of a general method to design multivalued circuits (Doctorat-es-Sciences).

1979-1981

• Examination of possible use of multivalued circuits and design of multivalued integrated circuits. Examination of interconnection issues when going from LSI to VLSI.

1981-1984

• Design of different integrated circuits including a 1-KB 4-valued ROM that was fabricated and operational when tested.

1984-1994

Multivalued circuits were only part of the on-going research. During this period, MVL activities include + Design of a 4-valued BiCMOS encoder and decoder circuits for transmission. The circuit was fabricated and operational when tested + Design of a 4-valued BiCMOS encoder and decoder circuits for transmission + Design of different 4-valued adders in CMOS and ECL technologies + Algorithms and circuits for 4-valued current-mode multi-operand addition.

I then decide to stop working on MVL circuits considering them as a dead end

From 1974 to 1994, I have presented 23 communications on Multivalued Logic Circuits in the following international conferences: International Symposium on Multiple Valued Logic (18), Fault Tolerant Computing Symposium (1), Compcon Spring(1), Compcon Fall (1), ESSIRC (1), Computer Arithmetic Conference (1) and 7 papers in the following international journals: Computer (1), IEEE Transactions on Computers (2), IEEE J. Solid State Circuits (1), IEICE Transactions on Information and Systems (1), Euromicro Journal (1), Digital Processes (1).

Most significant papers:

• Implementation of ternary circuits with binary integrated circuits
• Comparison of binary and multivalued integrated circuits according to VLSI criteria
• On the Performance of Multivalued Integrated Circuits: Past, Present and Future
• A 4-valued ECL Encoder and Decoder Circuit
• Why M-Valued Circuits are restricted to a Small Niche, in Journal of Multiple Valued Logic and Soft Computing, Volume 9, N°1, 2003.

Since 2019

I decided to revisit multivalued circuits to understand a basic contradiction:

• The only significant use of digital MVL circuits are the 4-valued or 8-valued flash memories in which larger access times are compensated by reduced chip area.
• At the same time, tens of ternary or quaternary circuits have been published using CNTFET tehnologies.

As Moore's law is still there and new technical progresses for binary circuits are regularly announced and implemented, the question is: why so many papers are published?

Common fallacies on ternary and quaternary digital circuits

Most MVL papers claim a lot of assumptions:

• Radix 3 is supposed to be the best radix
• MVL circuits are supposed to reduce interconnect, to reduce power dissipation, to reduce chip area, to be faster than the binary ones

A detailed examination shows that these assumptions are false, as shown in the following papers:

• Ternary circuits: why R=3 is not the Optimal Radix for Computation
• Ternary and Quaternary CNTFET Full Adders areless efficient than the Binary ones for Carry-Propagate Adders
• Comparing Unbalanced and Balanced CNTFET Ternary Adders and Multipliers with the Corresponding Binary Ones

Some other papers are available on ArXiv

Why m-valued circuits are better when m=2?

• All the simulations show that the ternary or quaternary circuits are less efficient than the binary ones. However, assuming a perfect gain when switching from m=2 to m=3 or m=4, this gain would be limited to log(3)/log2=1.585 or log(4)/log(2)=2.
• It turns out that a significant change in technologies or in computing paradigm occurs when and only when there is at least an order of magnitude in performance improvement. Quantum technology versus semiconductor technology is a good example. Using GPU as a coprocessor of CPU is another good example.