**Most significant papers** (insert crumbs.html here) # Multivalued circuits Presented in the [MVL section](MVL.html). ## FP16 Avec Lionel Lassagne, nous avons été parmi les premiers à publier des articles sur les flottants 16 bits (half de la norme IEEE 754) + [**16-bit floating point operations for low-end and high-end embedded processors**](https://largo.lip6.fr/~lacas/Publications/ODES05.pdf) + [**16-bit floating point instructions for embedded multimedia applications**](https://ieeexplore.ieee.org/document/1508186) + [**16-bit FP sub-word parallelism to facilitate compiler vectorization and improve performance of image and media processing**](https://largo.lip6.fr/~lacas/Publications/ICPP04.pdf) + [**Efficient 16-bit Floating-Point Interval Processor for Embedded Systems and Applications**](https://largo.lip6.fr/~lacas/Publications/SCAN06.pdf) + [**Customizing 16-bit floating point instructions on a NIOS II processor for FPGA image and media processing**](https://ieeexplore.ieee.org/document/1518073) Un papier récent montre l'intérêt des FP16 pour le flot optique. + [**Optical flow algorithms optimized for speed, energy and accuracy on embedded GPUs**](https://link.springer.com/article/10.1007/s11554-023-01288-6 et https://largo.lip6.fr/~lacas/Publications/JRTIP23_OpticalFlow.pdf) ## Parallel programming + [**MPI versus MPI+OpenMP on the IBM SP for the NAS Benchmarks, Supercomputing 2000**](https://ieeexplore.ieee.org/document/1592725, 118 cited in papers) + [**Parallel Smith-Waterman Comparison on Multicore and Manycore Computing Platforms with BSP++**](https://link.springer.com/article/10.1007/s10766-012-0209-6) + [**Parallel biological sequence comparison on heterogeneous high performance platforms with BSP++**](https://ieeexplore.ieee.org/document/6106015) + [**Algorithmic Skeletons within an Embedded Domain Specific Language for the CELL Processor**](https://ieeexplore.ieee.org/document/5260551) + [**Impact of high level transforms on high level synthesis for motion detection algorithm**](https://ieeexplore.ieee.org/document/6385388) + [**Hybrid bulk synchronous parallelism library for clustered smp architectures**](https://dl.acm.org/doi/abs/10.1145/1863482.1863494) ## Optical flow and Connected component labeling + [**Parallel Light Speed Labeling: an efficient connected component algorithm for labeling and analysis on multi-core processors**](https://link.springer.com/article/10.1007/s11554-016-0574-2) + [**Optical flow algorithms optimized for speed, energy and accuracy on embedded GPUs**](https://link.springer.com/article/10.1007/s11554-023-01288-6) + [**Parallel Light Speed Labeling: an Efficient Connected Component Labeling Algorithm for Multi-Core Processors**](https://ieeexplore.ieee.org/abstract/document/7351452) + [**A new SIMD iterative connected component labeling algorithm**](https://dl.acm.org/doi/10.1145/2870650.2870652) + [**Distanceless Label Propagation: an Efficient Direct Connected Component Labeling Algorithm for GPUs**](https://ieeexplore.ieee.org/document/8310147) ## Impact of technologies and ISA features on computer architectures and computer performances + [**45-year CPU evolution: one law and two equations**](https://arxiv.org/abs/1803.00254) + [**Technologies and Computing Paradigms: Beyond Moore's law?**](https://arxiv.org/abs/2206.03201) + [**Embedded MRAM for High-speed Computing**](https://ieeexplore.ieee.org/document/6081627) + [**Numerical Applications and Sub-Word Parallelism: The NAS Benchmarks on a Pentium 4**](https://dl.acm.org/doi/abs/10.5555/582787.822973)