DEGREES

Born on August 31 1947 in France.

Married, 3 children born on 1976, 1981 and 1988

• French baccalaureate in June 1965 (Good, >14/20)
• Engineer degree in Electrical Engineering from INSTITUT NATIONAL DES SCIENCES APPLIQUÉES DE LYON (French high school) in 1969.
• Engineer doctor thesis in Computer Science in June 1974 (Paris 6 university): “Study and model of logic circuits, applied to low level TTL”
• State Thesis (“doctorat-es-sciences”) in Computer Science in June 1979 (Paris 6 university): “Design and Use of multivalued logic circuits”.

EMPLOYEMENT POSITIONS

• Assistant professor in Paris 6 University (Paris) in Computer Science from October 1969 to April 1983.
• Professor in Paris 6 University from April 1983 to September 1988
• Professor in Paris Sud University (Orsay) from October 1988 to September 2000.
• Visiting professor in HP Labs (Palo Alto) from October 1998 to January 1999.
• Professor in University of Toronto from October 2000 to August 2002.
• Professor in Paris Sud University (Orsay) from September 2002 to September 2014
• Emeritus professor (Paris Sud, Paris Saclay) from Octobe 2014 to September 2024

TEACHING

Domains

• Computer architecture
• Computer hardware and logic design
• VLSI design
• Parallel architectures

Books and book translations

• Translation of the 2nd edition of “Computer Organization” (Hamacher, Vranesic and Zaky) with Michel Israel,
• Translation of the first edition of “Computer Architecture: a quantitative approach” by Hennessy and Patterson with Michel Israel (1991)
• Translation of the second (1996) and third editions of “Computer Architecture: a quantitative approach” by Hennessy and Patterson.
• Translation of upgrades of 8th and 9th editions of “Electronic Principes” by Malvino and Bates
• Translation of “FPGA design” by P. Simpson (2014)
• “Architecture of RISC processors” (in French), Armand Colin, 1991

RESEARCH

TOPICS

My research interests are at the intersection of microelectronics (hardware for computing and VLSI design) and computer science (Performance evaluation of CPU, memory hierarchies and computer architectures). They include

• VLSI design of binary and multivalued circuits in various technologies
• Impact of VLSI technologies on computer architectures and computer performances
• Performance of memory hierarchies in PC implementations
• Performance evaluation of interconnection networks for parallel and distributed architectures
• Computer arithmetic
• Program optimization for high performance and embedded processors

RESULTS

• 3 patents
• 11 publications in refereed international journals, including IEEE Transactions on Computer (2), IEEE Computer (1), IEEE Journal of Solid State Circuits (1), Journal of Parallel and distributed computing (1), TCS (1), Future Generation Computer System (1)
• 7 publications in refereed French journals TSI (6), Revue de Physique Appliquée (1)
• 58 publications in refereed International Conferences, including International Symposium on Multiple Valued Logic (18), Fault Tolerant Computing Symposium (1), Compcon Spring(1), Compcon Fall (1), ESSIRC (1), Design Automation Conference (1), ICCD(1), IEEE Bipolar Technology and Circuits Meeting (2), Euromicro (5), International Conference on Parallel Processing (1), International Parallel Computing Technologies Conference (3), Computer Arithmetic Conference (1), HPCA (1), SC (1), PACT (1) etc.
• 13 publications in Refereed French Conferences.

PH. D. STUDENTS

I have been supervisors for 26 Ph. D thesis and 1 Doctorat-es-Sciences between 1983 and 2007.

RESEARCH ORGANIZATION

• Program chairman for the PARLE conference (Parallel Architectures and Languages Europe) in Paris in 1992.
• Member of the program committee of the TSI French journal.
• Reviewer for many journals: IEEE Computer, IEEE Journal of Solid State Circuits, IEEE Micro, IEE Electronic Letters... and conferences ISMVL, FTC, CAC, Micro, etc.

ADMINISTRATION

INTERNATIONAL LEVEL

• Associate Editor of the IEEE Transactions on Computers from July 1999 to September 2002.
• IEEE Computer society representative for IFIP Technical Committee 10 from July 1999 to September 2009.

FRENCH LEVEL

• Member of the advisory board of the French CNRS Silicon Integrated Circuit Consortium from 1980 to 1993
• Chairman of the French National Coordinating Program in Computer Architecture (PRC ANM) from October 1992 to September 1996.
• Chairman of the Program Committee of ANR on “Future computer architectures” in 2006 and 2007.
• Member of the National Council of Universities (Computer Sciences) from 2003 2010.
• Chairman of the National Council of Universities (Computer Sciences) from 2007 to 2010.

UNIVERSITY LEVEL

• Chairman of the Computer Science Department in Paris 6 university from January 1986 to September 1988.
• Chairman of the Computer Science department in Paris Sud (Orsay) from October 1995 to September 1998.

News

** This is the last version (2024) of my WEB site.😅